SYNTHESIZE
Method of the pwar object.
Generates the VHDL files describing the digital circuit which implements the pwar function.
Contents
Description
This method automatically generates the VHDL files for the FPGA implementation of a digital architecture which computes the value of the pwar function.
Syntax
object = synthesize(object,circuit_parameters,[options])
The pwar object is returned as output because it is modified inside the method. circuit_parameters is a structure with the following fields:
- nbit - number of bits used to code input, output and memory values
- archtype - string defining the type of architecture to be employed, type 'A' which uses a multiply-and-accumulate (MAC) block to generate the output, or type 'B' which uses separate multipliers and an adder block. For further details, see [Comaschi et al., 2012].
- device - (optional) specifies the device (FPGA model) in which the circuit will be downloaded. This information is required by the Xilinx synthesis tool. See method xilinx for further details.
It is possible to specify further options for the synthesis process. options is a structure with the following fields:
- folder - destination folder where the VHDL files are saved (default is pwag_circuit_date, where date is subtitued with the current date in the format yyyy-mm-dd).
- test - boolean value; if set to 1 a testfile with input values on a grid on the domain is written to verify the VHDL code.
- samples - number of samples to use for each axis for the values in the testfile.
- xilinx - boolean value; if set to 1 a Xilinx ISE project is automatically created in the folder [options.folder '/ISE'].
Acknowledgements
Contributors:
- Bart Genuit (b.a.g.genuit@tue.nl)
- Alberto Oliveri (alberto.oliveri@unige.it)
- Tomaso Poggi (tomaso.poggi@unige.it)
Copyright is with:
- Copyright (C) 2012 Eindhoven University of Technology, The Netherlands.
- Copyright (C) 2010-2011 University of Genoa, Italy.