SYNTHESIZE
Generates the VHDL files describing the digital circuit implementing the pwas virtual sensor
Contents
Method of virtualsensor object.
Description
This method generates automatically the VHDL files for the implementation of a pwas virtual sensor. The circuit is made of several blocks implementing a pwas function whose outputs are summed together. The estimate of the unmeasurable output is possibly brought back to input if the virtual sensor is dynamical.
In order to map into a fixed point architecture, all the values are rescaled and quantized: if you want the circuit to compute the estimate given a point x, you must give to the circuit the value A x + B. The result f given by the circuit must be transformed into alpha f + beta, in order to come back to the original domain. x --> A x + B, f --> alpha f + beta. The values A, B, alpha and beta are stored in a structure synthesisInfo, property of the pwas object. They can be retrieved by using method getSynthesisInfo. The structure also stores the number of bits used to represent data in the circuit and other useful information (see method getSynthesisInfo).
Two circuit architectures are available: a serial one, employing a Multiply and Accumulate block and a parallel one employing as many multipliers as the number of dimensions of the domain plus one.
A log file is also generated in which the circuit performances are reported.
Syntax
object = synthesize(object,circuit_parameters,[options])
The vs object is returned as output because it is modified inside the method. circuit_parameters is a structure with the following fields:
- nbit: number of bits used to code inputs (default nbit = 12)
- nbit_coeff: number of bits used to code the value of the function in the vertices of the dimplicial partition (default nbit_coeff = nbit)
- type: string defining the type of architecture to be employed, parallel ('parallel') or serial ('serial'). Default type = 'serial'.
- frequency: indicates the frequency (in Hz) at which the circuit will work. Default frequency = 20000000 (20 MHz).
- samplingTime: indicates the sampling time of the circuit, i.e. the time between one input acquisition and the following one. If not provided it is set to the minimum available.
- z0: initial condition for the estimate z
It is possible to specify further options for the synthesis process. options is a structure with the following fields:
- folder: destination folder where the VHDL files are saved (default is vs_ser_circuit or vs_par_circuit followed by a progressive number).
Acknowledgements
Contributors:
- Alberto Oliveri (alberto.oliveri@unige.it)
Copyright is with:
- Copyright (C) 2012 University of Genoa, Italy.