Generates the VHDL files describing the digital circuit implementing the pwag function
Method of pwag object.
This method generates automatically the VHDL files for the implementation of a digital architecture which computes the value of the pwag function. The digital architecture is based on a binary search tree. If the tree is not available for the function (it can be computed in advance with method computeTree) it is automatically computed.
In order to map into a fixed point architecture, all the values (inputs, matrices) are rescaled and quantized: if you want the circuit to compute the value of the pwag function in a point x, you must give to the circuit the value A x + B. The result f given by the circuit must be multiplied for a scalar alpha in order to come back to the original domain. x --> A x + B, f --> alpha f. The values A, B and alpha are stored in a structure synthesisInfo, property of the pwag object. They can be retrieved by using method getSynthesisInfo. The structure also stores the number of bits used to represent data in the circuit and other useful information (see method getSynthesisInfo).
Two circuit architectures are available: a serial one, employing a Multiply and Accumulate block and a parallel one employing as many multipliers as the number of dimensions of the domain. Three different methods for the acquisition of the inputs can be chosen for both architectures: serial bitwise (at each clock cycle, one bit of all input components is read), serial component-wise (at each clock cycle a whole component of the input point is read) or parallel (all components of the input point are read in parallel).
A log file is also generated in which the circuit performances are reported.
object = synthesize(object,circuit_parameters,[options])
The pwag object is returned as output because it is modified inside the method. circuit_parameters is a structure with the following fields:
- nbit: number of bits used to code inputs and coefficients (default nbit = 12)
- nbit_coeff: number of bits used to code the coefficients in memory
- nbitout: number of bits used to code the value of the pwag function. If not provided it is chosen automatically in order to avoid truncation and overflow.
- type: string defining the type of architecture to be employed, parallel ('parallel') or serial ('serial'). Default type = 'serial'.
- inputAcquisition: string defining the input acquisition method to be employed: serial bitwise ('serial_bit'), serial component-wise ('serial_component') or parallel ('parallel'). Default inputAcquisition = 'parallel'.
- serialMode: needed only if input acquisition is serial bitwise. It is a string indicating if the input points are read starting from Most Significant Bit to Least Significant Bit ('MSB2LSB') or from Least Significant Bit to Most Significant Bit ('LSB2MSB'). Default serialMode = 'MSB3LSB'.
- frequency: indicates the frequency (in Hz) at which the circuit will work. Default frequency = 20000000 (20 MHz).
- samplingTime: indicates the sampling time of the circuit, i.e. the time between one input acquisition and the following one. If not provided it is set to the minimum available.
- provideOutput: indicates when to output the value of the pwag function. If provideOutput is set to 'asap', the value of the pwag function is provided as soon as it is ready; if it is set to 'alap', the value of the pwag function is provided when the following input point is read.
It is possible to specify further options for the synthesis process. options is a structure with the following fields:
- folder: destination folder where the VHDL files are saved (default is pwag_ser_circuit or pwag_par_circuit followed by a progressive number).
- Alberto Oliveri (firstname.lastname@example.org)
Copyright is with:
- Copyright (C) 2011 University of Genoa, Italy.